The push to sub-0.18 micron multilevel metallized interconnections, such as lines, via, and trenches, and the desire to produce faster semiconductor devices, has resulted in a shift toward the use of copper for making electrical interconnections in ultra-large scale integration circuits. The deposition of copper interconnects are not without difficulties, however. For example, when copper is etched, it tends to be redeposited elsewhere on the semiconductor device, or on the processing chamber. Copper atoms also readily diffuse into silicon-containing dielectric layers. The contamination by copper in unwanted locations can degrade or destroy the performance of active devices in integrated circuits.
One approach to reducing the problems with copper etching and diffusion to deposit an underlying barrier layer to block the migration of copper atoms into other components of the semiconductor. To facilitate the adhesion of copper to the diffusion barrier, a seed layer of copper is deposited over the diffusion barrier, followed by the deposition of a second thicker copper-conducting layer over the copper seed layer.
In a typical back-end-of-line integration flow an interlayer or intra-metal insulating layer is deposited on a semiconductor wafer and patterned to form lines, via, and trenches openings. The wafer is then transferred to one or more photoresist cleaning tools and then transferred to a tool for barrier and seed layer deposition. Typically, the diffusion barrier and copper seed layer are deposited on the wafer by a vacuum process, such as physical vapor deposition (PVD). The thick copper-conducting layer is deposited by a wet process, such as electrochemical deposition (ECD).
Because the wafer cleaning and barrier layer deposition are done on different tools, the wafer is exposed to the atmosphere for a period before being transferred to the deposition tool. Backlogs and mismatches in the machine times for wafer cleaning and seed layer deposition, or deposition tool break-down, can extend this period to several hours or even days. When processing of the wafer is resumed after extended periods barrier layer deposition is associated with delamination of the insulating layer or barrier layer from the wafer.
Accordingly, what is needed in the art is a method of forming a barrier layer that minimizes delamination and can accommodate a delay between post-patterning wafer cleaning and barrier layer deposition.